Field of the Invention
The present application relates to the technical field of display panels, and particularly, to a thin film transistor and a method of manufacturing the same, an array substrate, and a display panel.
Description of the Related Art A thin film transistor liquid crystal display (TFT-LCD) is a mainstream display in the current market of flat panel display due to its advantages such as small volume, light weight, low power consumption, availability in manufacturing a large-sized panel, no radiation or the like. TFT-LCD is mainly consisted of a TFT substrate and a color filter (CF) substrate, wherein the TFT substrate comprises an array of pixels, each of which being controlled by one TFT so as to display an image. The array of pixels may be formed by repeatedly performing processes such as thin film coating/deposition, exposure with mask, etching and the like.
Each pixel generally comprises TFT(s), a pixel electrode, a common electrode, a gate line, a data line and the like. Connections between electrodes are different for different display modes. Taking a HADS product as an example, as shown in FIG. 1, which is a top view of a pixel unit of a display panel in prior arts and shows following parts: a gate line 91 connected with a gate, a first common electrode 1022, a data line 93 connected with a drain electrode of a TFT, a source electrode line 94 connected with a source electrode of the TFT, an active layer 104 of the TFT, a second common electrode 108, and a via hole 98 through which the first common electrode is connected with the second common electrode. FIG. 2 is a section view taken along line A1-A2 and line D1-D2. As can be seen from FIG. 2, the gate 1021, a gate insulating layer 103, the active layer 104, a pixel electrode 105, the drain electrode 1062, the source electrode 1061, a passivation layer 107, and the second common electrode 108 located on the passivation layer are formed on a base substrate successively from the bottom up, wherein the first common electrode 1022 is also located in a same layer as the gate and is connected with the second common electrode 108 through the via hole 98. The via hole 98 has a depth equal to a sum of thicknesses of the gate insulating layer and the passivation layer. Thus, the depth of the via hole is generally larger, which will lead to defects associated therewith. For example, since the depth of the via hole is generally larger, a poor lapping connection will be likely caused and disconnection will be formed when an angle of slope of the via hole is larger, resulting in bright spot(s) in displayed images; further, the deeper via hole will likely result in uneven spreading in PI coating, which will form defects that cause greater adverse effects on the displayed images.
To sum up, only one via hole is used to achieve connection between the first common electrode and the second common electrode in the existing thin film transistor, and the depth of the via hole is equal to the sum of thicknesses of the gate insulating layer and the passivation layer and thus is larger, which results in lower success ratio for lapping connection between the second common electrode and the first common electrode, thereby aggravating the phenomenon where defective pixel(s) occurs in the display panel during PI coating.